1. Technology Field
The present invention relates to an apparatus and method for error simulation simulating by injecting an error and computing an error rate when a digital circuit is designed to have fault tolerant feature.
2. Description of the Related Art
A digital circuit may cause errors due to alpha particles, heat, low operating voltage and etc. Such errors further lead operating fails or faults of the digital circuit depending on the situation. Since such errors are fatal to the digital circuit, it requires an error preventing device to prevent them. It also requires a simulation device to test the performance of the error preventing device which is expected to reduce error occurrences when the error preventing device is applied to a system.
Unlike an analog circuit, a digital circuit implements desired functions by delivering 0 or 1. An error in a digital circuit may inverse output of an element or a cell composing the digital circuit at 0 or 1. This error occurred thereby is classified into immortal SEU and SET. SET causes errors to nodes of the digital circuit due to alpha particles, heat or, low operating voltage and the like but such errors disappear as time goes. SEU is the case where an error is maintained to a next state change by changing a sequential logic state. A simulation device to detect occurrence of errors caused by SET/SEU is required to determine and verify the performance of a part having a fault tolerant feature. In addition, the simulation device is also required for a system to which the part having a fault tolerant feature is applied.